In memory circuits, the individual memory cells are commonly organized into an array of rows and columns. The columns of memory cells in the array are associated with respective bitlines which act as an input/output ports for the cells in the respective columns. The rows of the array are associated with respective wordlines which are used to select a row of cells in the array. During a typical memory access, the appropriate wordline for a particular row of memory cells is selected, and the bitline corresponding to a column of the array containing a specific memory cell is used to access that cell. The bitline is connected to a sense amplifier which is constructed to sense the state of the selected memory cell and provide an amplified signal representing the sensed logic state to the next stage in the memory circuit.
In a static RAM circuit the memory cells commonly provide complementary outputs, and consequently complementary bitlines are usually available as input to a sense amplifier. For these applications a differential sense amplifier can conveniently be employed to sense the difference in signal levels on the complementary bitlines in order to determine the logic state of a memory cell. However, other forms of memory circuit, such as a floating-gate EPROM circuit, ordinarily provide only a single output is provided from each cell, i.e. only a single bitline for each array column. This arrangement is more space efficient, but makes sensing the cell state more difficult since a differential signal is not available. One way in which a sense amplifier for a memory array of this type can be operate is as a `pseudo-differential` amplifier circuit, wherein one differential input senses the state of the array memory cell and the other differential input is coupled to a dummy memory cell in a predetermined state. Thus, in a pseudo-differential sense amplifier, the input received by the amplifier is a difference signal representing the state of the array cell being sensed as compared to the predetermined state of the dummy cell.
One prior art pseudo-differential sense amplifier circuit 5 is diagramatically represented in FIG. 2. The prior art sense amplifier 5 comprises an input stage 10, a differential stage 40, and an output stage 60. The input stage 10 comprises a pair,of cascode circuits, namely an array side cascode circuit 12 and a reference side cascode circuit 25. The array side cascode circuit 12 is coupled by an array bitline to an array memory cell 24, whilst the reference side cascode circuit is coupled by a dummy bitline to a dummy memory cell 35. The input stage 10 provides differential inputs DIFFIN and DIFFREF to the differential stage 40, which in turn produces an amplified differential output to the output stage 60. The output stage 60 converts the differential signal from the differential stage to a logic level signal OUT, to be passed, for example, to an output buffer of the memory circuit containing the sense amplifier 5.
The prior art sense amplifier circuit 5 is designed such that the input stage reference side output voltage DIFFREF is between the array side output voltage DIFFIN for the array cell in the programmed state and the array cell in the erased state. This approach allows the circuit 5 to determine the state of the array cell based on whether the array side voltage DIFFIN is above or below the reference side voltage DIFFREF. In order to achieve this result the circuit 5 is constructed so as to carefully balance the voltages on the array and reference sides of the input stage 10 in order to meet the required voltage conditions for input to the differential stage 40. One consequence of this construction is that the cascode devices 16,29 on the array and reference sides of the input circuit must be different sizes. The different sized cascode devices introduces difficulties in operation of the sense amplifier under certain conditions, and can make the circuit susceptible to significant operational variations with variations in temperature, supply voltage and manufacturing process parameters. Another disadvantage of the prior art sense amplifier circuit 5 relates to glitches which can occur during power-on of the circuit.
Accordingly, it is an object of the present invention to at least substantially ameliorate some of the disadvantageous aspects of the prior art sense amplifier circuit. More particularly, it is an object of the invention to provide a pseudo-differential sense amplifier circuit which is less susceptible to erroneous switching and output glitches during activation of the sense amplifier. It is also an object of the invention to provide a pseudo-differential sense amplifier which is less susceptible to variations in process and operating conditions than the prior art.